blob: cb1f15224b45574a3c3d603566c859a9bec41937 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
|
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/spi/qcom,spi-qpic-snand.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm QPIC NAND controller
maintainers:
- Md sadre Alam <quic_mdalam@quicinc.com>
description:
The QCOM QPIC-SPI-NAND flash controller is an extended version of
the QCOM QPIC NAND flash controller. It can work both in serial
and parallel mode. It supports typical SPI-NAND page cache
operations in single, dual or quad IO mode with pipelined ECC
encoding/decoding using the QPIC ECC HW engine.
allOf:
- $ref: /schemas/spi/spi-controller.yaml#
properties:
compatible:
oneOf:
- items:
- enum:
- qcom,ipq5018-snand
- const: qcom,ipq9574-snand
- const: qcom,ipq9574-snand
reg:
maxItems: 1
clocks:
maxItems: 3
clock-names:
items:
- const: core
- const: aon
- const: iom
dmas:
items:
- description: tx DMA channel
- description: rx DMA channel
- description: cmd DMA channel
dma-names:
items:
- const: tx
- const: rx
- const: cmd
required:
- compatible
- reg
- clocks
- clock-names
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,ipq9574-gcc.h>
spi@79b0000 {
compatible = "qcom,ipq9574-snand";
reg = <0x1ac00000 0x800>;
clocks = <&gcc GCC_QPIC_CLK>,
<&gcc GCC_QPIC_AHB_CLK>,
<&gcc GCC_QPIC_IO_MACRO_CLK>;
clock-names = "core", "aon", "iom";
#address-cells = <1>;
#size-cells = <0>;
flash@0 {
compatible = "spi-nand";
reg = <0>;
#address-cells = <1>;
#size-cells = <1>;
nand-ecc-engine = <&qpic_nand>;
nand-ecc-strength = <4>;
nand-ecc-step-size = <512>;
};
};
|
