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path: root/tools/perf/pmu-events/arch/riscv/sifive/bullet/memory.json
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[
  {
    "EventName": "ICACHE_MISS",
    "EventCode": "0x102",
    "BriefDescription": "Counts instruction cache misses"
  },
  {
    "EventName": "DCACHE_MISS",
    "EventCode": "0x202",
    "BriefDescription": "Counts data cache misses"
  },
  {
    "EventName": "DCACHE_RELEASE",
    "EventCode": "0x402",
    "BriefDescription": "Counts writeback requests from the data cache"
  },
  {
    "EventName": "ITLB_MISS",
    "EventCode": "0x802",
    "BriefDescription": "Counts Instruction TLB misses caused by instruction address translation requests"
  },
  {
    "EventName": "DTLB_MISS",
    "EventCode": "0x1002",
    "BriefDescription": "Counts Data TLB misses caused by data address translation requests"
  },
  {
    "EventName": "UTLB_MISS",
    "EventCode": "0x2002",
    "BriefDescription": "Counts Unified TLB misses caused by address translation requests"
  }
]