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| author | Arnd Bergmann <arnd@arndb.de> | 2025-07-22 21:39:34 +0200 |
|---|---|---|
| committer | Arnd Bergmann <arnd@arndb.de> | 2025-07-22 21:39:35 +0200 |
| commit | 0acf88fe853a00d465bc7509f1acfeb346e41761 (patch) | |
| tree | 403301ade1946ac600f192844afa837dbce29f9b | |
| parent | 3116e1d5c145faf7d39bfba0afd1d22e9546e470 (diff) | |
| parent | 203b862057d08fbabcd4e475707751c0f2a9258b (diff) | |
Merge tag 'socfpga_dts_updates_for_v6.17' of https://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux into soc/dt
SoCFPGA DTS updates for v6.17
- Fix dt_binding_check warnings
- agilex - f2s-free-clk
- stratix10 - rstmgr
- swvp - remove phy-addr, cpu1-start-addr and altr,modrst-offset
* tag 'socfpga_dts_updates_for_v6.17' of https://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux:
arm64: dts: altera: socfpga_stratix10: update internal oscillators
arm64: dts: socfpga: swvp: remove phy-addr in the GMAC node
arm64: dts: socfpga: swvp: remove cpu1-start-addr
arm64: dts: socfpga: swvp: remove altr,modrst-offset
arm64: dts: socfpga: stratix10: fix dtbs_check for rstmgr
arm64: dts: socfpga: agilex: fix dtbs_check warning for f2s-free-clk
Link: https://lore.kernel.org/r/20250712123248.16981-1-dinguyen@kernel.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
| -rw-r--r-- | arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi | 5 | ||||
| -rw-r--r-- | arch/arm64/boot/dts/altera/socfpga_stratix10_swvp.dts | 6 | ||||
| -rw-r--r-- | arch/arm64/boot/dts/intel/socfpga_agilex.dtsi | 1 |
3 files changed, 5 insertions, 7 deletions
diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi index 0def0b0daaf7..effd242f6bf7 100644 --- a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi +++ b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi @@ -130,16 +130,19 @@ cb_intosc_hs_div2_clk: cb-intosc-hs-div2-clk { #clock-cells = <0>; compatible = "fixed-clock"; + clock-frequency = <150000000>; }; cb_intosc_ls_clk: cb-intosc-ls-clk { #clock-cells = <0>; compatible = "fixed-clock"; + clock-frequency = <300000000>; }; f2s_free_clk: f2s-free-clk { #clock-cells = <0>; compatible = "fixed-clock"; + status = "disabled"; }; osc1: osc1 { @@ -395,7 +398,7 @@ rst: rstmgr@ffd11000 { #reset-cells = <1>; - compatible = "altr,stratix10-rst-mgr"; + compatible = "altr,stratix10-rst-mgr", "altr,rst-mgr"; reg = <0xffd11000 0x1000>; }; diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10_swvp.dts b/arch/arm64/boot/dts/altera/socfpga_stratix10_swvp.dts index 34ccf8138f7b..ad52e8a0b9ba 100644 --- a/arch/arm64/boot/dts/altera/socfpga_stratix10_swvp.dts +++ b/arch/arm64/boot/dts/altera/socfpga_stratix10_swvp.dts @@ -68,7 +68,6 @@ &gmac1 { status = "okay"; phy-mode = "rgmii"; - phy-addr = <0xffffffff>; }; &gmac2 { @@ -103,12 +102,7 @@ status = "okay"; }; -&rst { - altr,modrst-offset = <0x20>; -}; - &sysmgr { reg = <0xffd12000 0x1000>; interrupts = <0x0 0x10 0x4>; - cpu1-start-addr = <0xffd06230>; }; diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi index a77a504effea..c1e66db0f4c5 100644 --- a/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi +++ b/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi @@ -126,6 +126,7 @@ f2s_free_clk: f2s-free-clk { #clock-cells = <0>; compatible = "fixed-clock"; + clock-frequency = <100000000>; }; osc1: osc1 { |