diff options
| author | Akshata Jahagirdar <akshata.jahagirdar@intel.com> | 2024-08-02 07:12:03 -0700 |
|---|---|---|
| committer | Matt Roper <matthew.d.roper@intel.com> | 2024-08-02 14:31:04 -0700 |
| commit | 2009e808bc3e0df6d4d83e2271bc25ae63a4ac05 (patch) | |
| tree | db2a77e07d48173073f5d5c1d9812639c80ae40c | |
| parent | 4f04d07c0a94b0b30db839e44f1b8364a1b508ac (diff) | |
drm/xe/xe2: Introduce performance changes
Add Compression Performance Improvement Changes in Xe2
v2: Rebase
v3: Rebase, updated as per latest changes on bspec,
Removed unnecessary default actions (Matt)
formatting nits (Tejas)
v4: Formatting nits, removed default set action for bit 14 (Matt)
Bspec: 72161
Signed-off-by: Akshata Jahagirdar <akshata.jahagirdar@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/c2dd753fdc55df6a6432026f2df9c2684a0d25c1.1722607628.git.akshata.jahagirdar@intel.com
| -rw-r--r-- | drivers/gpu/drm/xe/regs/xe_gt_regs.h | 3 | ||||
| -rw-r--r-- | drivers/gpu/drm/xe/xe_tuning.c | 5 |
2 files changed, 8 insertions, 0 deletions
diff --git a/drivers/gpu/drm/xe/regs/xe_gt_regs.h b/drivers/gpu/drm/xe/regs/xe_gt_regs.h index 3b87f95f9ecf..c50643ab4c84 100644 --- a/drivers/gpu/drm/xe/regs/xe_gt_regs.h +++ b/drivers/gpu/drm/xe/regs/xe_gt_regs.h @@ -367,6 +367,9 @@ #define XEHP_L3NODEARBCFG XE_REG_MCR(0xb0b4) #define XEHP_LNESPARE REG_BIT(19) +#define L3SQCREG2 XE_REG_MCR(0xb104) +#define COMPMEMRD256BOVRFETCHEN REG_BIT(20) + #define L3SQCREG3 XE_REG_MCR(0xb108) #define COMPPWOVERFETCHEN REG_BIT(28) diff --git a/drivers/gpu/drm/xe/xe_tuning.c b/drivers/gpu/drm/xe/xe_tuning.c index 77d4eec0118d..3817b7743b0c 100644 --- a/drivers/gpu/drm/xe/xe_tuning.c +++ b/drivers/gpu/drm/xe/xe_tuning.c @@ -45,6 +45,11 @@ static const struct xe_rtp_entry_sr gt_tunings[] = { XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, XE_RTP_END_VERSION_UNDEFINED)), XE_RTP_ACTIONS(SET(L3SQCREG3, COMPPWOVERFETCHEN)) }, + { XE_RTP_NAME("Tuning: L2 Overfetch Compressible Only"), + XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, XE_RTP_END_VERSION_UNDEFINED)), + XE_RTP_ACTIONS(SET(L3SQCREG2, + COMPMEMRD256BOVRFETCHEN)) + }, {} }; |