diff options
| author | Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> | 2024-11-01 11:57:16 +0200 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2024-11-03 12:29:51 +0100 |
| commit | 23c44956bce5aa79c060fc3e5d51843735e6eda6 (patch) | |
| tree | 938102cf9a9aa20a6abf22332679929c61e19577 | |
| parent | 75f3dec9a4d971ae71a491229340a0911e9c23f6 (diff) | |
arm64: dts: renesas: r9a08g045: Add VBATTB node
Add the DT node for the VBATTB IP along with DT bindings for the clock
it provides.
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Link: https://lore.kernel.org/20241101095720.2247815-6-claudiu.beznea.uj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| -rw-r--r-- | arch/arm64/boot/dts/renesas/r9a08g045.dtsi | 19 |
1 files changed, 19 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi index 067a26a66c24..a1d5084b074a 100644 --- a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi @@ -72,6 +72,18 @@ status = "disabled"; }; + vbattb: clock-controller@1005c000 { + compatible = "renesas,r9a08g045-vbattb"; + reg = <0 0x1005c000 0 0x1000>; + interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD R9A08G045_VBAT_BCLK>, <&vbattb_xtal>; + clock-names = "bclk", "rtx"; + #clock-cells = <1>; + power-domains = <&cpg>; + resets = <&cpg R9A08G045_VBAT_BRESETN>; + status = "disabled"; + }; + i2c0: i2c@10090000 { compatible = "renesas,riic-r9a08g045", "renesas,riic-r9a09g057"; reg = <0 0x10090000 0 0x400>; @@ -425,4 +437,11 @@ interrupt-names = "sec-phys", "phys", "virt", "hyp-phys", "hyp-virt"; }; + + vbattb_xtal: vbattb-xtal { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board. */ + clock-frequency = <0>; + }; }; |