diff options
| author | Mihai Sain <mihai.sain@microchip.com> | 2025-06-19 10:06:35 +0300 |
|---|---|---|
| committer | Claudiu Beznea <claudiu.beznea@tuxon.dev> | 2025-07-05 10:43:30 +0300 |
| commit | 4101c8274b093519019761e174c81980f7b30f56 (patch) | |
| tree | b096c39c1b52dd315ff6f5c8aca1bc9d697ce0d2 | |
| parent | 1e2e0ed390cc3c074817b2026a59da008b6cd2a6 (diff) | |
ARM: dts: microchip: sama7d65: Add cache configuration for cpu node
Describe the cache memories according with datasheet chapter 15.2:
- L1 cache configuration with 32KB for both data and instruction cache.
- L2 cache configuration with 256KB unified cache.
Before this patch the kernel reported the warning:
[ 0.161955] cacheinfo: Unable to detect cache hierarchy for CPU 0
Signed-off-by: Mihai Sain <mihai.sain@microchip.com>
Link: https://lore.kernel.org/r/20250619070636.8844-2-mihai.sain@microchip.com
Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
| -rw-r--r-- | arch/arm/boot/dts/microchip/sama7d65.dtsi | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/microchip/sama7d65.dtsi b/arch/arm/boot/dts/microchip/sama7d65.dtsi index 7f3d67099b7d..c191acc2c89f 100644 --- a/arch/arm/boot/dts/microchip/sama7d65.dtsi +++ b/arch/arm/boot/dts/microchip/sama7d65.dtsi @@ -32,6 +32,16 @@ device_type = "cpu"; clocks = <&pmc PMC_TYPE_CORE PMC_CPUPLL>; clock-names = "cpu"; + d-cache-size = <0x8000>; // L1, 32 KB + i-cache-size = <0x8000>; // L1, 32 KB + next-level-cache = <&L2>; + + L2: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-size = <0x40000>; // L2, 256 KB + cache-unified; + }; }; }; |