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authorAlessandro Ratti <alessandro@0x65c.net>2025-08-15 17:37:26 +0200
committerJason Gunthorpe <jgg@nvidia.com>2025-08-18 11:15:06 -0300
commit447c6141e8ea68ef4e56c55144fd18f43e6c8dca (patch)
treea2cef39959d2b37564bbece7b23466907bca3f53
parent8fe8a092043f28d3c8e467cb2bbfe1e1ccf7f996 (diff)
iommufd: Fix spelling errors in iommufd.rst
This patch corrects two minor spelling issues found in Documentation/userspace-api/iommufd.rst: - "primarly" -> "primarily" - "sharable" -> "shareable" Found using codespell(1). Link: https://patch.msgid.link/r/20250815153840.188213-2-alessandro@0x65c.net Signed-off-by: Alessandro Ratti <alessandro@0x65c.net> Signed-off-by: Jason Gunthorpe <jgg@nvidia.com>
-rw-r--r--Documentation/userspace-api/iommufd.rst4
1 files changed, 2 insertions, 2 deletions
diff --git a/Documentation/userspace-api/iommufd.rst b/Documentation/userspace-api/iommufd.rst
index 03f7510384d2..f1c4d21e5c5e 100644
--- a/Documentation/userspace-api/iommufd.rst
+++ b/Documentation/userspace-api/iommufd.rst
@@ -43,7 +43,7 @@ Following IOMMUFD objects are exposed to userspace:
- IOMMUFD_OBJ_HWPT_PAGING, representing an actual hardware I/O page table
(i.e. a single struct iommu_domain) managed by the iommu driver. "PAGING"
- primarly indicates this type of HWPT should be linked to an IOAS. It also
+ primarily indicates this type of HWPT should be linked to an IOAS. It also
indicates that it is backed by an iommu_domain with __IOMMU_DOMAIN_PAGING
feature flag. This can be either an UNMANAGED stage-1 domain for a device
running in the user space, or a nesting parent stage-2 domain for mappings
@@ -76,7 +76,7 @@ Following IOMMUFD objects are exposed to userspace:
* Security namespace for guest owned ID, e.g. guest-controlled cache tags
* Non-device-affiliated event reporting, e.g. invalidation queue errors
- * Access to a sharable nesting parent pagetable across physical IOMMUs
+ * Access to a shareable nesting parent pagetable across physical IOMMUs
* Virtualization of various platforms IDs, e.g. RIDs and others
* Delivery of paravirtualized invalidation
* Direct assigned invalidation queues