diff options
| author | Neeraj Upadhyay <Neeraj.Upadhyay@amd.com> | 2025-08-28 16:32:41 +0530 |
|---|---|---|
| committer | Borislav Petkov (AMD) <bp@alien8.de> | 2025-09-01 12:21:55 +0200 |
| commit | 45e2cef568cdf87cb06c9783b45c8f08d1ab1cec (patch) | |
| tree | 0486ce610dbaef8d79d9e9a91eb51200f0e9b60b | |
| parent | c822f58a4fab25944ba66768c1d6c563aa6ac077 (diff) | |
x86/apic: Initialize APIC ID for Secure AVIC
Initialize the APIC ID in the Secure AVIC APIC backing page with the APIC_ID
MSR value read from the hypervisor. CPU topology evaluation later during boot
would catch and report any duplicate APIC ID for two CPUs.
Signed-off-by: Neeraj Upadhyay <Neeraj.Upadhyay@amd.com>
Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de>
Reviewed-by: Tianyu Lan <tiala@microsoft.com>
Link: https://lore.kernel.org/20250828110255.208779-2-Neeraj.Upadhyay@amd.com
| -rw-r--r-- | arch/x86/kernel/apic/x2apic_savic.c | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/arch/x86/kernel/apic/x2apic_savic.c b/arch/x86/kernel/apic/x2apic_savic.c index 5479605429c1..56c51ea4e5ab 100644 --- a/arch/x86/kernel/apic/x2apic_savic.c +++ b/arch/x86/kernel/apic/x2apic_savic.c @@ -150,6 +150,12 @@ static void savic_setup(void) enum es_result res; unsigned long gpa; + /* + * Before Secure AVIC is enabled, APIC MSR reads are intercepted. + * APIC_ID MSR read returns the value from the hypervisor. + */ + apic_set_reg(ap, APIC_ID, native_apic_msr_read(APIC_ID)); + gpa = __pa(ap); /* |