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authorMrinmay Sarkar <quic_msarkar@quicinc.com>2024-03-11 19:41:37 +0530
committerBjorn Andersson <andersson@kernel.org>2024-05-27 12:03:58 -0500
commit4b220c6fa9f379cb8803dbca73ae1f4128dfa5c8 (patch)
treeda2dbef22367c21a91aa412185dab04436104070
parentbfc10ebd76d56e3bf8899891e5730604eea46db4 (diff)
arm64: dts: qcom: sa8775p: Mark PCIe EP controller as cache coherent
The PCIe EP controller on SA8775P supports cache coherency, hence add the "dma-coherent" property to mark it as such. Signed-off-by: Mrinmay Sarkar <quic_msarkar@quicinc.com> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/1710166298-27144-4-git-send-email-quic_msarkar@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
-rw-r--r--arch/arm64/boot/dts/qcom/sa8775p.dtsi1
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
index dcb2d8435d47..5632fa896b93 100644
--- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi
+++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
@@ -4649,6 +4649,7 @@
<&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_0 0>;
interconnect-names = "pcie-mem", "cpu-pcie";
+ dma-coherent;
iommus = <&pcie_smmu 0x0000 0x7f>;
resets = <&gcc GCC_PCIE_0_BCR>;
reset-names = "core";