diff options
| author | Pengyu Luo <mitltlatltl@gmail.com> | 2025-04-05 18:55:28 +0800 |
|---|---|---|
| committer | Bjorn Andersson <andersson@kernel.org> | 2025-05-14 21:46:08 +0100 |
| commit | 4becd72352b6861de0c24074a8502ca85080fd63 (patch) | |
| tree | 043b3f64ad0f517f752e4964b220801c8cc6ecb6 | |
| parent | d12fbd11c5a3e98c2f6372252bf84b0e10dd91cc (diff) | |
arm64: dts: qcom: sm8650: add the missing l2 cache node
Only two little a520s share the same L2, every a720 has their own L2
cache.
Fixes: d2350377997f ("arm64: dts: qcom: add initial SM8650 dtsi")
Signed-off-by: Pengyu Luo <mitltlatltl@gmail.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20250405105529.309711-1-mitltlatltl@gmail.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
| -rw-r--r-- | arch/arm64/boot/dts/qcom/sm8650.dtsi | 9 |
1 files changed, 8 insertions, 1 deletions
diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qcom/sm8650.dtsi index c2937f721794..495ea9bfd008 100644 --- a/arch/arm64/boot/dts/qcom/sm8650.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi @@ -188,7 +188,7 @@ power-domain-names = "psci"; enable-method = "psci"; - next-level-cache = <&l2_200>; + next-level-cache = <&l2_300>; capacity-dmips-mhz = <1792>; dynamic-power-coefficient = <238>; @@ -204,6 +204,13 @@ &epss_l3 SLAVE_EPSS_L3_SHARED>; #cooling-cells = <2>; + + l2_300: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-unified; + next-level-cache = <&l3_0>; + }; }; cpu4: cpu@400 { |