diff options
| author | Wolfram Sang <wsa+renesas@sang-engineering.com> | 2025-06-04 10:40:11 +0200 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2025-06-19 19:34:33 +0200 |
| commit | 52c34f57fc81f2317a60ed55e2b6ca6ecdb1efdc (patch) | |
| tree | 9059329f798e6cd8b28011b49ea2c5d1f7bbef01 | |
| parent | 4f6780c14fea09bc56c4991d6bf8f2a594bfb51f (diff) | |
ARM: dts: renesas: r9a06g032: Add second clock input to RTC
The external RTC clock is populated on the RZ/N1D module, so describe it
and add a reference to the RTC node.
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250604084211.28090-2-wsa+renesas@sang-engineering.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| -rw-r--r-- | arch/arm/boot/dts/renesas/r9a06g032-rzn1d400-db.dts | 4 | ||||
| -rw-r--r-- | arch/arm/boot/dts/renesas/r9a06g032.dtsi | 4 |
2 files changed, 6 insertions, 2 deletions
diff --git a/arch/arm/boot/dts/renesas/r9a06g032-rzn1d400-db.dts b/arch/arm/boot/dts/renesas/r9a06g032-rzn1d400-db.dts index d734a432b3ec..3258b2e27434 100644 --- a/arch/arm/boot/dts/renesas/r9a06g032-rzn1d400-db.dts +++ b/arch/arm/boot/dts/renesas/r9a06g032-rzn1d400-db.dts @@ -171,6 +171,10 @@ renesas,miic-switch-portin = <MIIC_GMAC2_PORT>; }; +&ext_rtc_clk { + clock-frequency = <32768>; +}; + &gmac2 { status = "okay"; phy-mode = "gmii"; diff --git a/arch/arm/boot/dts/renesas/r9a06g032.dtsi b/arch/arm/boot/dts/renesas/r9a06g032.dtsi index 80ad1fdc77a0..13a60656b044 100644 --- a/arch/arm/boot/dts/renesas/r9a06g032.dtsi +++ b/arch/arm/boot/dts/renesas/r9a06g032.dtsi @@ -73,8 +73,8 @@ <GIC_SPI 67 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 68 IRQ_TYPE_EDGE_RISING>; interrupt-names = "alarm", "timer", "pps"; - clocks = <&sysctrl R9A06G032_HCLK_RTC>; - clock-names = "hclk"; + clocks = <&sysctrl R9A06G032_HCLK_RTC>, <&ext_rtc_clk>; + clock-names = "hclk", "xtal"; power-domains = <&sysctrl>; status = "disabled"; }; |