diff options
| author | Atish Patra <atishp@rivosinc.com> | 2025-05-15 16:11:18 -0700 |
|---|---|---|
| committer | Anup Patel <anup@brainfault.org> | 2025-05-21 09:34:55 +0530 |
| commit | 5bc40978675241aad7175fadc857262118588805 (patch) | |
| tree | 6449d27540e861030ebc221f993da3ff26332827 | |
| parent | 9f0e6b98c1a13ac1f38d559b548b8f122572ae18 (diff) | |
RISC-V: KVM: Remove scounteren initialization
Scounteren CSR controls the direct access the hpmcounters and cycle/
instret/time from the userspace. It's the supervisor's responsibility
to set it up correctly for it's user space. They hypervisor doesn't
need to decide the policy on behalf of the supervisor.
Signed-off-by: Atish Patra <atishp@rivosinc.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
Link: https://lore.kernel.org/r/20250515-fix_scounteren_vs-v3-1-729dc088943e@rivosinc.com
Signed-off-by: Anup Patel <anup@brainfault.org>
| -rw-r--r-- | arch/riscv/kernel/head.S | 10 | ||||
| -rw-r--r-- | arch/riscv/kvm/vcpu.c | 3 |
2 files changed, 10 insertions, 3 deletions
diff --git a/arch/riscv/kernel/head.S b/arch/riscv/kernel/head.S index 356d5397b2a2..bdf3352acf4c 100644 --- a/arch/riscv/kernel/head.S +++ b/arch/riscv/kernel/head.S @@ -131,6 +131,12 @@ secondary_start_sbi: csrw CSR_IE, zero csrw CSR_IP, zero +#ifndef CONFIG_RISCV_M_MODE + /* Enable time CSR */ + li t0, 0x2 + csrw CSR_SCOUNTEREN, t0 +#endif + /* Load the global pointer */ load_global_pointer @@ -226,6 +232,10 @@ SYM_CODE_START(_start_kernel) * to hand it to us. */ csrr a0, CSR_MHARTID +#else + /* Enable time CSR */ + li t0, 0x2 + csrw CSR_SCOUNTEREN, t0 #endif /* CONFIG_RISCV_M_MODE */ /* Load the global pointer */ diff --git a/arch/riscv/kvm/vcpu.c b/arch/riscv/kvm/vcpu.c index a78f9ec2fa0e..a7188e007db9 100644 --- a/arch/riscv/kvm/vcpu.c +++ b/arch/riscv/kvm/vcpu.c @@ -79,9 +79,6 @@ static void kvm_riscv_vcpu_context_reset(struct kvm_vcpu *vcpu) cntx->hstatus |= HSTATUS_VTW; cntx->hstatus |= HSTATUS_SPVP; cntx->hstatus |= HSTATUS_SPV; - - /* By default, make CY, TM, and IR counters accessible in VU mode */ - csr->scounteren = 0x7; } static void kvm_riscv_reset_vcpu(struct kvm_vcpu *vcpu) |