diff options
| author | Akshay Gupta <Akshay.Gupta@amd.com> | 2021-07-26 19:06:15 +0530 |
|---|---|---|
| committer | Guenter Roeck <linux@roeck-us.net> | 2021-08-17 14:54:25 -0700 |
| commit | 60b76c3a117ce076f60f58de17bae1122849746a (patch) | |
| tree | 768d7fdcbde2cda713566d60d3f131e45e876112 | |
| parent | 04165fb73f9b8ea9e5cc2f3c21ca2a777516fc7b (diff) | |
dt-bindings: sbrmi: Add SB-RMI hwmon driver bindings
- Document device tree bindings for AMD SB-RMI emulated service.
Signed-off-by: Akshay Gupta <Akshay.Gupta@amd.com>
Signed-off-by: Naveen Krishna Chatradhi <nchatrad@amd.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20210726133615.9709-3-nchatrad@amd.com
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
| -rw-r--r-- | Documentation/devicetree/bindings/hwmon/amd,sbrmi.yaml | 53 |
1 files changed, 53 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/hwmon/amd,sbrmi.yaml b/Documentation/devicetree/bindings/hwmon/amd,sbrmi.yaml new file mode 100644 index 000000000000..7598b083979c --- /dev/null +++ b/Documentation/devicetree/bindings/hwmon/amd,sbrmi.yaml @@ -0,0 +1,53 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/hwmon/amd,sbrmi.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: > + Sideband Remote Management Interface (SB-RMI) compliant + AMD SoC power device. + +maintainers: + - Akshay Gupta <Akshay.Gupta@amd.com> + +description: | + SB Remote Management Interface (SB-RMI) is an SMBus compatible + interface that reports AMD SoC's Power (normalized Power) using, + Mailbox Service Request and resembles a typical 8-pin remote power + sensor's I2C interface to BMC. The power attributes in hwmon + reports power in microwatts. + +properties: + compatible: + enum: + - amd,sbrmi + + reg: + maxItems: 1 + description: | + I2C bus address of the device as specified in Section SBI SMBus Address + of the SoC register reference. The SB-RMI address is normally 78h for + socket 0 and 70h for socket 1, but it could vary based on hardware + address select pins. + \[open source SoC register reference\] + https://www.amd.com/en/support/tech-docs?keyword=55898 + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + i2c0 { + #address-cells = <1>; + #size-cells = <0>; + + sbrmi@3c { + compatible = "amd,sbrmi"; + reg = <0x3c>; + }; + }; +... |