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authorBarnabás Czémán <barnabas.czeman@mainlining.org>2025-08-30 23:13:20 +0200
committerBjorn Andersson <andersson@kernel.org>2025-09-01 13:03:31 -0500
commit690bc19286407cf1c0fc189910a936261ae1344c (patch)
tree59cea72fe1838b62d2ab80aab7aff296fef5c89b
parent4faee358fea854fddba95843c55d9eb9013a4f00 (diff)
arm64: dts: qcom: msm8953: correct SPI pinctrls
SPI pinctrls should handle 4 pins MOSI, MISO, CLK and CS. This change adding the missing pins for pinctrls and correcting CS pins according to downstream sources. Fixes: be69109e93c78 ("arm64: dts: qcom: msm8953: add SPI interfaces") Signed-off-by: Barnabás Czémán <barnabas.czeman@mainlining.org> Link: https://lore.kernel.org/r/20250830-msm8953-spi-fix-v1-2-89950eaf10fe@mainlining.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
-rw-r--r--arch/arm64/boot/dts/qcom/msm8953.dtsi102
1 files changed, 78 insertions, 24 deletions
diff --git a/arch/arm64/boot/dts/qcom/msm8953.dtsi b/arch/arm64/boot/dts/qcom/msm8953.dtsi
index 14dd17278ae0..1b3e68aed945 100644
--- a/arch/arm64/boot/dts/qcom/msm8953.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8953.dtsi
@@ -775,45 +775,99 @@
};
spi_3_default: spi-3-default-state {
- pins = "gpio10", "gpio11";
- function = "blsp_spi3";
- drive-strength = <2>;
- bias-disable;
+ cs-pins {
+ pins = "gpio10";
+ function = "blsp_spi3";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ spi-pins {
+ pins = "gpio8", "gpio9", "gpio11";
+ function = "blsp_spi3";
+ drive-strength = <12>;
+ bias-disable;
+ };
};
spi_3_sleep: spi-3-sleep-state {
- pins = "gpio10", "gpio11";
- function = "gpio";
- drive-strength = <2>;
- bias-disable;
+ cs-pins {
+ pins = "gpio10";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ spi-pins {
+ pins = "gpio8", "gpio9", "gpio11";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
};
spi_5_default: spi-5-default-state {
- pins = "gpio18", "gpio19";
- function = "blsp_spi5";
- drive-strength = <2>;
- bias-disable;
+ cs-pins {
+ pins = "gpio18";
+ function = "blsp_spi5";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ spi-pins {
+ pins = "gpio16", "gpio17", "gpio19";
+ function = "blsp_spi5";
+ drive-strength = <12>;
+ bias-disable;
+ };
};
spi_5_sleep: spi-5-sleep-state {
- pins = "gpio18", "gpio19";
- function = "gpio";
- drive-strength = <2>;
- bias-disable;
+ cs-pins {
+ pins = "gpio18";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ spi-pins {
+ pins = "gpio16", "gpio17", "gpio19";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
};
spi_6_default: spi-6-default-state {
- pins = "gpio22", "gpio23";
- function = "blsp_spi6";
- drive-strength = <2>;
- bias-disable;
+ cs-pins {
+ pins = "gpio22";
+ function = "blsp_spi6";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ spi-pins {
+ pins = "gpio20", "gpio21", "gpio23";
+ function = "blsp_spi6";
+ drive-strength = <12>;
+ bias-disable;
+ };
};
spi_6_sleep: spi-6-sleep-state {
- pins = "gpio22", "gpio23";
- function = "gpio";
- drive-strength = <2>;
- bias-disable;
+ cs-pins {
+ pins = "gpio22";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ spi-pins {
+ pins = "gpio20", "gpio21", "gpio23";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
};
uart_5_default: uart-5-default-state {