diff options
| author | Qiang Yu <qiang.yu@oss.qualcomm.com> | 2025-07-22 17:11:50 +0800 |
|---|---|---|
| committer | Bjorn Andersson <andersson@kernel.org> | 2025-08-11 16:43:07 -0500 |
| commit | 6facfaff0fe3b4d5903bed6164eb5e60ee6cdb8f (patch) | |
| tree | d351e5638482b614ed0f686ddd23bc188d7134ab | |
| parent | f93e5882134a314760d47536d93b57fbd32d0da1 (diff) | |
arm64: dts: qcom: x1e80100: add bus topology for PCIe domain 3
Add pcie3_port node to represent the PCIe bridge of PCIe3 so that PCI slot
voltage rails can be described under this node in the board's dts.
Signed-off-by: Qiang Yu <qiang.yu@oss.qualcomm.com>
Signed-off-by: Wenbin Yao <quic_wenbyao@quicinc.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20250722091151.1423332-3-quic_wenbyao@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
| -rw-r--r-- | arch/arm64/boot/dts/qcom/x1e80100.dtsi | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi index 5e9a8fa3cf96..c9fea040223b 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi @@ -3306,6 +3306,17 @@ opp-peak-kBps = <15753000 1>; }; }; + + pcie3_port: pcie@0 { + device_type = "pci"; + compatible = "pciclass,0604"; + reg = <0x0 0x0 0x0 0x0 0x0>; + bus-range = <0x01 0xff>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; }; pcie3_phy: phy@1be0000 { |