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authorQuentin Schulz <quentin.schulz@cherry.de>2025-02-18 12:49:19 +0100
committerHeiko Stuebner <heiko@sntech.de>2025-02-23 00:44:37 +0100
commit83c247e2bc1bb7bde2e54ab3767421e22a06ff77 (patch)
tree48b8a967577970c1359334c623c62c18eb51143b
parentf65f71a4c33706146ca81822ed08319d6740d343 (diff)
arm64: dts: rockchip: enable I2C3 in Haikou carrierboard, not Ringneck DTSI
PX30 Ringneck only exposes I2C3 as LVDS_BLC_CLK/DAT on Q7 golden fingers but nothing is on that bus on the SoM itself. Therefore, let's enable the I2C3 bus where it makes sense, in the Haikou carrierboard DTS. Signed-off-by: Quentin Schulz <quentin.schulz@cherry.de> Link: https://lore.kernel.org/r/20250218-tsd-align-haikou-v1-8-5c44d1dd8658@cherry.de Signed-off-by: Heiko Stuebner <heiko@sntech.de>
-rw-r--r--arch/arm64/boot/dts/rockchip/px30-ringneck-haikou.dts2
-rw-r--r--arch/arm64/boot/dts/rockchip/px30-ringneck.dtsi4
2 files changed, 2 insertions, 4 deletions
diff --git a/arch/arm64/boot/dts/rockchip/px30-ringneck-haikou.dts b/arch/arm64/boot/dts/rockchip/px30-ringneck-haikou.dts
index e4517f47d519..16996cc6b8b6 100644
--- a/arch/arm64/boot/dts/rockchip/px30-ringneck-haikou.dts
+++ b/arch/arm64/boot/dts/rockchip/px30-ringneck-haikou.dts
@@ -154,6 +154,8 @@
};
&i2c3 {
+ status = "okay";
+
eeprom@50 {
reg = <0x50>;
compatible = "atmel,24c01";
diff --git a/arch/arm64/boot/dts/rockchip/px30-ringneck.dtsi b/arch/arm64/boot/dts/rockchip/px30-ringneck.dtsi
index ae050cc6cd05..c166a9e3cc1c 100644
--- a/arch/arm64/boot/dts/rockchip/px30-ringneck.dtsi
+++ b/arch/arm64/boot/dts/rockchip/px30-ringneck.dtsi
@@ -325,10 +325,6 @@
};
};
-&i2c3 {
- status = "okay";
-};
-
&i2s0_8ch {
rockchip,trcm-sync-tx-only;