diff options
| author | Oleksij Rempel <o.rempel@pengutronix.de> | 2023-01-31 09:46:31 +0100 |
|---|---|---|
| committer | Shawn Guo <shawnguo@kernel.org> | 2023-03-06 10:01:46 +0800 |
| commit | 887185649c7ee8a9cc2d4e94de92bbbae6cd3747 (patch) | |
| tree | 36d0ab78869b4c1d5a490b5c9bb9cf3e23b508d7 | |
| parent | 5417c655b98ed385d18695a9fbb384883a0d1f47 (diff) | |
ARM: dts: imx6dl-plym2m: configure ethernet reference clock parent
On this board the PHY is the ref clock provider. So, configure ethernet
reference clock as input.
Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
| -rw-r--r-- | arch/arm/boot/dts/imx6dl-plym2m.dts | 12 |
1 files changed, 8 insertions, 4 deletions
diff --git a/arch/arm/boot/dts/imx6dl-plym2m.dts b/arch/arm/boot/dts/imx6dl-plym2m.dts index 522660c912a0..e3c10483f33b 100644 --- a/arch/arm/boot/dts/imx6dl-plym2m.dts +++ b/arch/arm/boot/dts/imx6dl-plym2m.dts @@ -84,6 +84,7 @@ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <50000000>; + clock-output-names = "enet_ref_pad"; }; reg_3v3: regulator-3v3 { @@ -173,6 +174,13 @@ status = "okay"; }; +&clks { + clocks = <&clk50m_phy>; + clock-names = "enet_ref_pad"; + assigned-clocks = <&clks IMX6QDL_CLK_ENET_REF_SEL>; + assigned-clock-parents = <&clk50m_phy>; +}; + &ecspi1 { cs-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>; pinctrl-names = "default"; @@ -254,10 +262,6 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_enet>; phy-mode = "rmii"; - clocks = <&clks IMX6QDL_CLK_ENET>, - <&clks IMX6QDL_CLK_ENET>, - <&clk50m_phy>; - clock-names = "ipg", "ahb", "ptp"; phy-handle = <&rgmii_phy>; status = "okay"; |