diff options
| author | Maxime Ripard <maxime.ripard@free-electrons.com> | 2015-10-12 22:21:49 +0200 |
|---|---|---|
| committer | Maxime Ripard <maxime.ripard@free-electrons.com> | 2015-10-21 22:43:25 +0200 |
| commit | 88a86aaa613032e0d5cf70a3d0777302ec2ed40b (patch) | |
| tree | 06628a666d19a6e8ebe6bfd1a2a0f5f128b68bf9 | |
| parent | 6f87abb8cd7dc00701f0a732962420fddbf4b79b (diff) | |
ARM: sun7i: Add audio PLL
The A20 uses the PLL2 as the audio PLL, which is the parent of all the
other audio clocks in the system (i2s, codec, etc.). Add it to the DTSI.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Chen-Yu Tsai <wens@csie.org>
| -rw-r--r-- | arch/arm/boot/dts/sun7i-a20.dtsi | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi index 3a68852f6706..433ec1415e56 100644 --- a/arch/arm/boot/dts/sun7i-a20.dtsi +++ b/arch/arm/boot/dts/sun7i-a20.dtsi @@ -199,6 +199,15 @@ clock-output-names = "pll1"; }; + pll2: clk@01c20008 { + #clock-cells = <1>; + compatible = "allwinner,sun4i-a10-pll2-clk"; + reg = <0x01c20008 0x8>; + clocks = <&osc24M>; + clock-output-names = "pll2-1x", "pll2-2x", + "pll2-4x", "pll2-8x"; + }; + pll4: clk@01c20018 { #clock-cells = <0>; compatible = "allwinner,sun7i-a20-pll4-clk"; |