diff options
author | Varadarajan Narayanan <quic_varada@quicinc.com> | 2024-11-21 10:49:35 +0530 |
---|---|---|
committer | Bjorn Andersson <andersson@kernel.org> | 2025-01-07 20:25:29 -0600 |
commit | 9e2ca54195af42bf2b52a5c6349e0a751b1828b1 (patch) | |
tree | f147f14b362d9065cb1161c648773c6df7cfac87 | |
parent | 256e6937e48a14cc5ea02ce9e4e0fbb4463c4464 (diff) |
arm64: dts: qcom: ipq5424: Add LLCC/system-cache-controller
Add a DT node for Last level cache (aka. system cache) controller
which provides control over the last level cache present on
IPQ5424 SoCs.
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
Link: https://lore.kernel.org/r/20241121051935.1055222-4-quic_varada@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
-rw-r--r-- | arch/arm64/boot/dts/qcom/ipq5424.dtsi | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/qcom/ipq5424.dtsi b/arch/arm64/boot/dts/qcom/ipq5424.dtsi index 5e79bd450a4e..3277e25d57f5 100644 --- a/arch/arm64/boot/dts/qcom/ipq5424.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq5424.dtsi @@ -152,6 +152,13 @@ clock-names = "core"; }; + system-cache-controller@800000 { + compatible = "qcom,ipq5424-llcc"; + reg = <0 0x00800000 0 0x200000>; + reg-names = "llcc0_base"; + interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; + }; + tlmm: pinctrl@1000000 { compatible = "qcom,ipq5424-tlmm"; reg = <0 0x01000000 0 0x300000>; |