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authorNaga Sureshkumar Relli <nagasuresh.relli@microchip.com>2022-08-08 12:16:00 +0530
committerMark Brown <broonie@kernel.org>2022-08-15 12:17:36 +0100
commita5890c12ecce2696f90ef7d2b8fbb33387f735de (patch)
tree72858a033f8e279082cfbb65cf3004f4440e7b74
parent75c971dd6c4ed6d0218ce52bfa4572a6dded7695 (diff)
spi: dt-binding: document microchip coreQSPI
Add microchip coreQSPI compatible string and update the title/description to reflect this addition. Signed-off-by: Naga Sureshkumar Relli <nagasuresh.relli@microchip.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20220808064603.1174906-2-nagasuresh.relli@microchip.com Signed-off-by: Mark Brown <broonie@kernel.org>
-rw-r--r--Documentation/devicetree/bindings/spi/microchip,mpfs-spi.yaml7
1 files changed, 6 insertions, 1 deletions
diff --git a/Documentation/devicetree/bindings/spi/microchip,mpfs-spi.yaml b/Documentation/devicetree/bindings/spi/microchip,mpfs-spi.yaml
index 7326c0a28d16..a47d4923b51b 100644
--- a/Documentation/devicetree/bindings/spi/microchip,mpfs-spi.yaml
+++ b/Documentation/devicetree/bindings/spi/microchip,mpfs-spi.yaml
@@ -4,7 +4,11 @@
$id: http://devicetree.org/schemas/spi/microchip,mpfs-spi.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
-title: Microchip MPFS {Q,}SPI Controller Device Tree Bindings
+title: Microchip FPGA {Q,}SPI Controllers
+
+description:
+ SPI and QSPI controllers on Microchip PolarFire SoC and the "soft"/
+ fabric IP cores they are based on
maintainers:
- Conor Dooley <conor.dooley@microchip.com>
@@ -17,6 +21,7 @@ properties:
enum:
- microchip,mpfs-spi
- microchip,mpfs-qspi
+ - microchip,coreqspi-rtl-v2 # FPGA QSPI
reg:
maxItems: 1