diff options
| author | Adrian Ng Ho Yin <adrianhoyin.ng@altera.com> | 2025-10-15 10:12:43 +0800 |
|---|---|---|
| committer | Dinh Nguyen <dinguyen@kernel.org> | 2025-11-04 15:25:44 -0600 |
| commit | aef9703dcbf8a816af06a30e51a0f9e3773086e3 (patch) | |
| tree | 06236bde8cf085f6b0fde4a7b7574b43d7373c71 | |
| parent | 3e99d51aaaba3ed3f092f635ad053fe1ca5953ff (diff) | |
arm64: dts: socfpga: agilex5: Add SMMU-V3-PMCG nodes
Add SMMU-V3 Performance Monitoring Counter Group (PMCG) nodes for
Agilex5 to support SMMU performance event monitoring.
Signed-off-by: Adrian Ng Ho Yin <adrianhoyin.ng@altera.com>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
| -rw-r--r-- | arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi | 62 |
1 files changed, 62 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi index f0379e4eac9d..408911ea7bc5 100644 --- a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi +++ b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi @@ -154,6 +154,12 @@ compatible = "usb-nop-xceiv"; }; + pmu0: pmu { + compatible = "arm,armv8-pmuv3"; + interrupt-parent = <&intc>; + interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; + }; + soc: soc@0 { compatible = "simple-bus"; ranges = <0 0 0 0xffffffff>; @@ -860,5 +866,61 @@ }; }; }; + + pmu0_tcu: pmu@16002000 { + compatible = "arm,smmu-v3-pmcg"; + reg = <0x16002000 0x1000>, + <0x16022000 0x1000>; + interrupt-parent = <&intc>; + interrupts = <GIC_SPI 136 IRQ_TYPE_EDGE_RISING>; + }; + + pmu0_tbu0: pmu@16042000 { + compatible = "arm,smmu-v3-pmcg"; + reg = <0x16042000 0x1000>, + <0x16052000 0x1000>; + interrupt-parent = <&intc>; + interrupts = <GIC_SPI 138 IRQ_TYPE_EDGE_RISING>; + }; + + pmu0_tbu1: pmu@16062000 { + compatible = "arm,smmu-v3-pmcg"; + reg = <0x16062000 0x1000>, + <0x16072000 0x1000>; + interrupt-parent = <&intc>; + interrupts = <GIC_SPI 140 IRQ_TYPE_EDGE_RISING>; + }; + + pmu0_tbu2: pmu@16082000 { + compatible = "arm,smmu-v3-pmcg"; + reg = <0x16082000 0x1000>, + <0x16092000 0x1000>; + interrupt-parent = <&intc>; + interrupts = <GIC_SPI 142 IRQ_TYPE_EDGE_RISING>; + }; + + pmu0_tbu3: pmu@160a2000 { + compatible = "arm,smmu-v3-pmcg"; + reg = <0x160A2000 0x1000>, + <0x160B2000 0x1000>; + interrupt-parent = <&intc>; + interrupts = <GIC_SPI 144 IRQ_TYPE_EDGE_RISING>; + }; + + pmu0_tbu4: pmu@160c2000 { + compatible = "arm,smmu-v3-pmcg"; + reg = <0x160C2000 0x1000>, + <0x160D2000 0x1000>; + interrupt-parent = <&intc>; + interrupts = <GIC_SPI 146 IRQ_TYPE_EDGE_RISING>; + }; + + pmu0_tbu5: pmu@160e2000 { + compatible = "arm,smmu-v3-pmcg"; + reg = <0x160E2000 0x1000>, + <0x160F2000 0x1000>; + interrupt-parent = <&intc>; + interrupts = <GIC_SPI 150 IRQ_TYPE_EDGE_RISING>; + }; }; }; |