diff options
| author | Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> | 2025-04-08 11:32:13 +0200 |
|---|---|---|
| committer | Bjorn Andersson <andersson@kernel.org> | 2025-04-08 16:56:16 -0500 |
| commit | b44bf3bc74912649b2495894e82f5384e24e2060 (patch) | |
| tree | c1e7ceb13e2f0392786b3a8a2e36147817c1df05 | |
| parent | 77764620c1888e8c8dc169f7c2f693fc4db96964 (diff) | |
arm64: dts: qcom: sm6115: Use the header with DSI phy clock IDs
Use the header with DSI phy clock IDs to make code more readable.
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20250408-dts-qcom-dsi-phy-clocks-v2-16-73b482a6dd02@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
| -rw-r--r-- | arch/arm64/boot/dts/qcom/sm6115.dtsi | 8 |
1 files changed, 5 insertions, 3 deletions
diff --git a/arch/arm64/boot/dts/qcom/sm6115.dtsi b/arch/arm64/boot/dts/qcom/sm6115.dtsi index 94c081bf7a89..55a0db0ed9cb 100644 --- a/arch/arm64/boot/dts/qcom/sm6115.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6115.dtsi @@ -3,6 +3,7 @@ * Copyright (c) 2021, Iskren Chernev <iskren.chernev@gmail.com> */ +#include <dt-bindings/clock/qcom,dsi-phy-28nm.h> #include <dt-bindings/clock/qcom,gcc-sm6115.h> #include <dt-bindings/clock/qcom,sm6115-dispcc.h> #include <dt-bindings/clock/qcom,sm6115-gpucc.h> @@ -1960,7 +1961,8 @@ assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; - assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>; + assigned-clock-parents = <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, + <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>; operating-points-v2 = <&dsi_opp_table>; power-domains = <&rpmpd SM6115_VDDCX>; @@ -2034,8 +2036,8 @@ reg = <0x0 0x05f00000 0 0x20000>; clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&sleep_clk>, - <&mdss_dsi0_phy 0>, - <&mdss_dsi0_phy 1>, + <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, + <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>, <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>; #clock-cells = <1>; #reset-cells = <1>; |