diff options
| author | Thomas Gleixner <tglx@linutronix.de> | 2025-11-19 18:26:49 +0100 |
|---|---|---|
| committer | Peter Zijlstra <peterz@infradead.org> | 2025-11-20 12:14:53 +0100 |
| commit | be4463fa2c7185823d2989562162d578b45a89ae (patch) | |
| tree | f0955daf833532d10d689eb1b3c092e8d3bd5462 | |
| parent | 8cea569ca785060b8c5cc7800713ddc3b1548a94 (diff) | |
sched/mmcid: Cacheline align MM CID storage
Both the per CPU storage and the data in mm_struct are heavily used in
context switch. As they can end up next to other frequently modified data,
they are subject to false sharing.
Make them cache line aligned.
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Reviewed-by: Mathieu Desnoyers <mathieu.desnoyers@efficios.com>
Link: https://patch.msgid.link/20251119172549.194111661@linutronix.de
| -rw-r--r-- | include/linux/rseq_types.h | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/include/linux/rseq_types.h b/include/linux/rseq_types.h index e444dd267c7a..d7e8071b626a 100644 --- a/include/linux/rseq_types.h +++ b/include/linux/rseq_types.h @@ -112,7 +112,7 @@ struct sched_mm_cid { */ struct mm_cid_pcpu { unsigned int cid; -}; +}____cacheline_aligned_in_smp; /** * struct mm_mm_cid - Storage for per MM CID data @@ -126,7 +126,7 @@ struct mm_mm_cid { struct mm_cid_pcpu __percpu *pcpu; unsigned int nr_cpus_allowed; raw_spinlock_t lock; -}; +}____cacheline_aligned_in_smp; #else /* CONFIG_SCHED_MM_CID */ struct mm_mm_cid { }; struct sched_mm_cid { }; |