diff options
| author | Unnathi Chalicheemala <quic_uchalich@quicinc.com> | 2024-05-31 09:45:26 -0700 |
|---|---|---|
| committer | Bjorn Andersson <andersson@kernel.org> | 2024-05-31 17:44:09 -0500 |
| commit | c566143137aaacfed1af09d8710edab1971c312d (patch) | |
| tree | e5bc1ef517753ce64f50c47683c4836a767f414b | |
| parent | 809c20b1ffc80200bfcbbeceb0d946a3e0eed3a4 (diff) | |
arm64: dts: qcom: sm8450: Add Broadcast_AND register in LLCC block
Chipsets before SM8450 have only one broadcast register (Broadcast_OR)
which is used to broadcast writes and check for status bit 0 only in
all channels.
>From SM8450 onwards, a new Broadcast_AND region was added which checks
for status bit 1. This hasn't been updated and Broadcast_OR region
was wrongly being used to check for status bit 1 all along.
Hence mapping Broadcast_AND region's address space to LLCC in SM8450.
Signed-off-by: Unnathi Chalicheemala <quic_uchalich@quicinc.com>
Link: https://lore.kernel.org/r/bfc817da4188abdf5b543bedafb9cb0eb82806c2.1717014052.git.quic_uchalich@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
| -rw-r--r-- | arch/arm64/boot/dts/qcom/sm8450.dtsi | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index fe9cb0804285..216f4f703643 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -4461,9 +4461,10 @@ compatible = "qcom,sm8450-llcc"; reg = <0 0x19200000 0 0x80000>, <0 0x19600000 0 0x80000>, <0 0x19300000 0 0x80000>, <0 0x19700000 0 0x80000>, - <0 0x19a00000 0 0x80000>; + <0 0x19a00000 0 0x80000>, <0 0x19c00000 0 0x80000>; reg-names = "llcc0_base", "llcc1_base", "llcc2_base", - "llcc3_base", "llcc_broadcast_base"; + "llcc3_base", "llcc_broadcast_base", + "llcc_broadcast_and_base"; interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>; }; |