diff options
| author | Shawn Lin <shawn.lin@rock-chips.com> | 2025-11-26 07:26:39 +0800 |
|---|---|---|
| committer | Ulf Hansson <ulf.hansson@linaro.org> | 2025-11-26 11:45:27 +0100 |
| commit | c7ce6453b769c45006ed4983762f81e130878171 (patch) | |
| tree | 08d1711180e3e31880130920927b0e5f31ae395c | |
| parent | e2bbd950eb726c29e3214a6b91a828de2cb770d9 (diff) | |
mmc: sdhci-of-dwcmshc: Disable internal clock auto gate for Rockchip SOCs
Enabling CMDQ support can lead to random occurrences of the error log when
there are RPMB access and data flush executed:
"mmc2: Timeout waiting for hardware interrupt."
Enabling CMDQ and then issuing a DCMD as the final command before disabling
it causes the eMMC controller to auto-gate its internal clock. Chip simulation
shows this results in a state machine mismatch after CMDQ mode exit, triggering
data-timeout errors for all subsequent read and write operations.
Therefore, the auto-clock-gate function must be disabled whenever CMDQ is
enabled.
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Acked-by: Adrian Hunter <adrian.hunter@intel.com>
Fixes: fda1e0af7c28 ("mmc: sdhci-of-dwcmshc: Add command queue support for rockchip SOCs")
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
| -rw-r--r-- | drivers/mmc/host/sdhci-of-dwcmshc.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/drivers/mmc/host/sdhci-of-dwcmshc.c b/drivers/mmc/host/sdhci-of-dwcmshc.c index 498997c8648f..36e7c0bec431 100644 --- a/drivers/mmc/host/sdhci-of-dwcmshc.c +++ b/drivers/mmc/host/sdhci-of-dwcmshc.c @@ -726,10 +726,11 @@ static void dwcmshc_rk3568_set_clock(struct sdhci_host *host, unsigned int clock sdhci_set_clock(host, clock); - /* Disable cmd conflict check */ + /* Disable cmd conflict check and internal clock gate */ reg = dwc_priv->vendor_specific_area1 + DWCMSHC_HOST_CTRL3; extra = sdhci_readl(host, reg); extra &= ~BIT(0); + extra |= BIT(4); sdhci_writel(host, extra, reg); if (clock <= 52000000) { |