diff options
| author | Suraj Kandpal <suraj.kandpal@intel.com> | 2025-11-01 08:54:49 +0530 |
|---|---|---|
| committer | Suraj Kandpal <suraj.kandpal@intel.com> | 2025-11-01 09:03:39 +0530 |
| commit | cff042eefe1a3583b890f66fb8f34f2f85b5b827 (patch) | |
| tree | 6e819aa29f66c7b230e519d36e4275e717966cd7 | |
| parent | 5298eea7ed209ff14aebce70ae11f212bab37f9f (diff) | |
drm/i915/ltphy: Add LT Phy related VDR and Pipe Registers
Add LT Phy related VDR and pipe registers into its own new file.
Bspec: 74500
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
Reviewed-by: Arun R Murthy <arun.r.murthy@intel.com>
Link: https://patch.msgid.link/20251101032513.4171255-2-suraj.kandpal@intel.com
| -rw-r--r-- | drivers/gpu/drm/i915/display/intel_lt_phy_regs.h | 24 |
1 files changed, 24 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy_regs.h b/drivers/gpu/drm/i915/display/intel_lt_phy_regs.h new file mode 100644 index 000000000000..6eaa038bf684 --- /dev/null +++ b/drivers/gpu/drm/i915/display/intel_lt_phy_regs.h @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: MIT + * + * Copyright © 2025 Intel Corporation + */ + +#ifndef __INTEL_LT_PHY_REGS_H__ +#define __INTEL_LT_PHY_REGS_H__ + +/* LT Phy Vendor Register */ +#define LT_PHY_VDR_0_CONFIG 0xC02 +#define LT_PHY_VDR_DP_PLL_ENABLE REG_BIT(7) +#define LT_PHY_VDR_1_CONFIG 0xC03 +#define LT_PHY_VDR_RATE_ENCODING_MASK REG_GENMASK8(6, 3) +#define LT_PHY_VDR_MODE_ENCODING_MASK REG_GENMASK8(2, 0) +#define LT_PHY_VDR_2_CONFIG 0xCC3 + +#define LT_PHY_VDR_X_ADDR_MSB(idx) (0xC04 + 0x6 * (idx)) +#define LT_PHY_VDR_X_ADDR_LSB(idx) (0xC05 + 0x6 * (idx)) + +#define LT_PHY_VDR_X_DATAY(idx, y) ((0xC06 + (3 - (y))) + 0x6 * (idx)) + +#define LT_PHY_RATE_UPDATE 0xCC4 + +#endif /* __INTEL_LT_PHY_REGS_H__ */ |