diff options
| author | Uwe Kleine-König <uwe@kleine-koenig.org> | 2025-03-18 22:08:46 +0100 |
|---|---|---|
| committer | Heiko Stuebner <heiko@sntech.de> | 2025-04-07 09:15:45 +0200 |
| commit | d01e09a9f7cd4fb5a947e3dc718242b51b581615 (patch) | |
| tree | 282ed14c83a5c6d3826ef15cfab21cecde1ba13b | |
| parent | 831263a4164e189c47e3a9ea189cb4b5bc078b1e (diff) | |
arm64: dts: rockchip: Add gmac phy reset GPIO to QNAP TS433
While looking through the vendor U-Boot code Heiko spotted that a SoC
GPIO is connected to the ethernet phy's reset pin. Add the respective
reset-gpios property with pinmuxing for the GPIO to the phy node.
Signed-off-by: Uwe Kleine-König <uwe@kleine-koenig.org>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Link: https://lore.kernel.org/r/49f66206fccc714a8745b9ac35247615ad5cc369.1742331667.git.ukleinek@kernel.org
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
| -rw-r--r-- | arch/arm64/boot/dts/rockchip/rk3568-qnap-ts433.dts | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/rockchip/rk3568-qnap-ts433.dts b/arch/arm64/boot/dts/rockchip/rk3568-qnap-ts433.dts index 70e88769e21c..411f8ac7994b 100644 --- a/arch/arm64/boot/dts/rockchip/rk3568-qnap-ts433.dts +++ b/arch/arm64/boot/dts/rockchip/rk3568-qnap-ts433.dts @@ -485,6 +485,10 @@ /* Motorcomm YT8521 phy */ compatible = "ethernet-phy-ieee802.3-c22"; reg = <0x3>; + pinctrl-0 = <ð_phy0_reset_pin>; + pinctrl-names = "default"; + reset-assert-us = <10000>; + reset-gpios = <&gpio0 RK_PC6 GPIO_ACTIVE_LOW>; }; }; @@ -557,6 +561,12 @@ }; &pinctrl { + gmac0 { + eth_phy0_reset_pin: eth-phy0-reset-pin { + rockchip,pins = <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + keys { copy_button_pin: copy-button-pin { rockchip,pins = <0 RK_PB6 RK_FUNC_GPIO &pcfg_pull_up>; |