diff options
| author | Inochi Amaoto <inochiama@gmail.com> | 2025-06-09 07:28:30 +0800 |
|---|---|---|
| committer | Inochi Amaoto <inochiama@gmail.com> | 2025-07-23 09:55:14 +0800 |
| commit | ddaa0b550022fd56167a592e23b9aa0b737753f5 (patch) | |
| tree | df89b4349d4e8e4308ea043637afe88e6b57aa5e | |
| parent | f88aa1f14c6bccd9a498f842ed16155fe3279b23 (diff) | |
riscv: dts: sophgo: sg2044: Add MMC controller device
Add emmc controller and sd controller DT node for SG2044.
Link: https://lore.kernel.org/r/20250608232836.784737-7-inochiama@gmail.com
Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
Signed-off-by: Chen Wang <wangchen20@iscas.ac.cn>
| -rw-r--r-- | arch/riscv/boot/dts/sophgo/sg2044-sophgo-srd3-10.dts | 17 | ||||
| -rw-r--r-- | arch/riscv/boot/dts/sophgo/sg2044.dtsi | 24 |
2 files changed, 41 insertions, 0 deletions
diff --git a/arch/riscv/boot/dts/sophgo/sg2044-sophgo-srd3-10.dts b/arch/riscv/boot/dts/sophgo/sg2044-sophgo-srd3-10.dts index 54cdf4239d5f..d077923097e8 100644 --- a/arch/riscv/boot/dts/sophgo/sg2044-sophgo-srd3-10.dts +++ b/arch/riscv/boot/dts/sophgo/sg2044-sophgo-srd3-10.dts @@ -27,6 +27,23 @@ clock-frequency = <25000000>; }; +&emmc { + bus-width = <4>; + no-sdio; + no-sd; + non-removable; + wp-inverted; + status = "okay"; +}; + +&sd { + bus-width = <4>; + no-sdio; + no-mmc; + wp-inverted; + status = "okay"; +}; + &uart1 { status = "okay"; }; diff --git a/arch/riscv/boot/dts/sophgo/sg2044.dtsi b/arch/riscv/boot/dts/sophgo/sg2044.dtsi index a4d2f8a13cc3..6067901cde1e 100644 --- a/arch/riscv/boot/dts/sophgo/sg2044.dtsi +++ b/arch/riscv/boot/dts/sophgo/sg2044.dtsi @@ -111,6 +111,30 @@ status = "disabled"; }; + emmc: mmc@703000a000 { + compatible = "sophgo,sg2044-dwcmshc", "sophgo,sg2042-dwcmshc"; + reg = <0x70 0x3000a000 0x0 0x1000>; + clocks = <&clk CLK_GATE_EMMC>, + <&clk CLK_GATE_AXI_EMMC>, + <&clk CLK_GATE_EMMC_100K>; + clock-names = "core", "bus", "timer"; + interrupt-parent = <&intc>; + interrupts = <298 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + sd: mmc@703000b000 { + compatible = "sophgo,sg2044-dwcmshc", "sophgo,sg2042-dwcmshc"; + reg = <0x70 0x3000b000 0x0 0x1000>; + clocks = <&clk CLK_GATE_SD>, + <&clk CLK_GATE_AXI_SD>, + <&clk CLK_GATE_SD_100K>; + clock-names = "core", "bus", "timer"; + interrupt-parent = <&intc>; + interrupts = <300 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + i2c0: i2c@7040005000 { compatible = "sophgo,sg2044-i2c", "snps,designware-i2c"; reg = <0x70 0x40005000 0x0 0x1000>; |