diff options
| author | Antonio Borneo <antonio.borneo@foss.st.com> | 2025-10-23 15:27:00 +0200 |
|---|---|---|
| committer | Alexandre Torgue <alexandre.torgue@foss.st.com> | 2025-11-14 09:33:12 +0100 |
| commit | e613ef5c1516b7b281f9f437598a6b3e320fffe1 (patch) | |
| tree | 2871860a2a49a7486708f9a2f26a82c77b8a829e | |
| parent | 22f0ae971cf5536349521853737d3e06203286d8 (diff) | |
arm64: dts: st: Add I/O sync to eth pinctrl in stm32mp25-pinctrl.dtsi
On board stm32mp257f-ev1, the propagation delay between eth1/eth2
and the external PHY requires a compensation to guarantee that no
packet get lost in all the working conditions.
Add I/O synchronization properties in pinctrl on all the RGMII
data pins, activating re-sampling on both edges of the clock.
Co-developed-by: Christophe Roullier <christophe.roullier@foss.st.com>
Signed-off-by: Christophe Roullier <christophe.roullier@foss.st.com>
Signed-off-by: Antonio Borneo <antonio.borneo@foss.st.com>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Link: https://lore.kernel.org/r/20251023132700.1199871-13-antonio.borneo@foss.st.com
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
| -rw-r--r-- | arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi b/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi index e0d102eb6176..c34cd33cd855 100644 --- a/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi +++ b/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi @@ -38,6 +38,7 @@ bias-disable; drive-push-pull; slew-rate = <3>; + st,io-sync = "data on both edges"; }; pins2 { pinmux = <STM32_PINMUX('H', 9, AF10)>, /* ETH_RGMII_CLK125 */ @@ -53,6 +54,7 @@ <STM32_PINMUX('H', 13, AF10)>, /* ETH_RGMII_RXD3 */ <STM32_PINMUX('A', 11, AF10)>; /* ETH_RGMII_RX_CTL */ bias-disable; + st,io-sync = "data on both edges"; }; pins4 { pinmux = <STM32_PINMUX('A', 14, AF10)>; /* ETH_RGMII_RX_CLK */ @@ -142,6 +144,7 @@ bias-disable; drive-push-pull; slew-rate = <3>; + st,io-sync = "data on both edges"; }; pins2 { pinmux = <STM32_PINMUX('F', 8, AF10)>, /* ETH_RGMII_CLK125 */ @@ -164,6 +167,7 @@ <STM32_PINMUX('C', 11, AF10)>, /* ETH_RGMII_RXD3 */ <STM32_PINMUX('C', 3, AF10)>; /* ETH_RGMII_RX_CTL */ bias-disable; + st,io-sync = "data on both edges"; }; pins5 { pinmux = <STM32_PINMUX('F', 6, AF10)>; /* ETH_RGMII_RX_CLK */ |