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authorDavidlohr Bueso <dave@stgolabs.net>2025-09-12 22:04:04 +0200
committerRafael J. Wysocki <rafael.j.wysocki@intel.com>2025-09-15 12:20:13 +0200
commiteddf12041ddd8c40289015f42285c5ac614b5c30 (patch)
tree8243736cd4c5d60400d49b17114b0e06cad553ea
parent8ca944fea4d6d9019e01f2d6f6e766f315a9d73f (diff)
ACPICA: CEDT: Add Back-Invalidate restriction to CXL Window
This is added in newer version (3.0+) of the CXL Spec to support the HDM-DB coherency model. Link: https://github.com/acpica/acpica/commit/a6886da1 Signed-off-by: Davidlohr Bueso <dave@stgolabs.net> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
-rw-r--r--include/acpi/actbl1.h1
1 files changed, 1 insertions, 0 deletions
diff --git a/include/acpi/actbl1.h b/include/acpi/actbl1.h
index 99fd1588ff38..0b4c332df25c 100644
--- a/include/acpi/actbl1.h
+++ b/include/acpi/actbl1.h
@@ -565,6 +565,7 @@ struct acpi_cedt_cfmws_target_element {
#define ACPI_CEDT_CFMWS_RESTRICT_VOLATILE (1<<2)
#define ACPI_CEDT_CFMWS_RESTRICT_PMEM (1<<3)
#define ACPI_CEDT_CFMWS_RESTRICT_FIXED (1<<4)
+#define ACPI_CEDT_CFMWS_RESTRICT_BI (1<<5)
/* 2: CXL XOR Interleave Math Structure */