diff options
| author | John Madieu <john.madieu.xa@bp.renesas.com> | 2025-05-19 00:08:12 +0200 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2025-05-26 12:07:27 +0200 |
| commit | f62bb41740462bf9fde4b110df5c7d3bc223fb3c (patch) | |
| tree | 914289a16aa486b612b823fd3c737cbcad2ebbcc | |
| parent | 652eea251dd852f02cef6223f367220acb3d1867 (diff) | |
arm64: dts: renesas: rzg3e-smarc-som: Reduce I2C2 clock frequency
Lower the I2C2 bus clock frequency on the RZ/G3E SMARC SoM from 1MHz to
400kHz to improve compatibility with a wider range of I2C peripherals.
As the GreenPAK device is programmed to operate at 400kHz, the previous
1MHz setting was too aggressive, causing it to experience timing issues.
Fixes: f7a98e256ee3 ("arm64: dts: renesas: rzg3e-smarc-som: Add I2C2 device pincontrol")
Signed-off-by: John Madieu <john.madieu.xa@bp.renesas.com>
Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250518220812.1480696-1-john.madieu.xa@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| -rw-r--r-- | arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi index 43d79158d81a..ecea29a76b14 100644 --- a/arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi @@ -85,7 +85,7 @@ &i2c2 { pinctrl-0 = <&i2c2_pins>; pinctrl-names = "default"; - clock-frequency = <1000000>; + clock-frequency = <400000>; status = "okay"; raa215300: pmic@12 { |