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| author | Teng Wu <gigadevice2025@gmail.com> | 2025-06-30 11:49:31 +0800 |
|---|---|---|
| committer | Miquel Raynal <miquel.raynal@bootlin.com> | 2025-07-30 11:27:30 +0200 |
| commit | fdfb040d0bc5963b7f107cc0711a62cd6ed1682c (patch) | |
| tree | 90361b981d80ceac8dda7e8b2695f9790c48b36c | |
| parent | 258ef75cf2e219350574c8a8d3695451c093ed38 (diff) | |
mtd: spinand: gigadevice: Add support for GD5F1GM9 chips
- GD5F1GM9UExxG (ID:c89101 3.3V)
- GD5F1GM9RExxG (ID:c88101 1.8V)
Both device feature:
- 1Gb density (1024 blocks)
- 2048-byte page size with 128-byte OOB
- 8-bit ECC requirement per 512 bytes
- Quad I/O Read support (opcode EBH)
- tPROG ≤ 300us typical page program time
Testing environment:
- Platform: Raspberry PI-5 (Linux raspberry 6.15.0-rc6-v8)
- Operations verified:
* Full device read/write/erase cycles on all blocks
* Nandspeed:
~ GD5F1GM9UE: 2.75MB/s read, 1.99MB/s write, 41.26MB/s erase
~ GD5F1GM9RE: 1.84MB/s read, 1.45MB/s write, 41.04MS/s erase
* Nandbiterrs: Both corredted 8-bit errors per 512 bytes
* Stresstest: Both 144k cycles 0 bad block growth
Full test log:
-U: https://gist.github.com/WT-886/b0f41fb50ddac3adc0020222c1f89b61
-R: https://gist.github.com/WT-886/8784e72f4632d519814928ff49225963
Datasheet:
-https://github.com/WT-886/DATASHEET/blob/main/GD5F1GM9-v1.0.pdf
Signed-off-by: Teng Wu <gigadevice2025@gmail.com>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
| -rw-r--r-- | drivers/mtd/nand/spi/gigadevice.c | 20 |
1 files changed, 20 insertions, 0 deletions
diff --git a/drivers/mtd/nand/spi/gigadevice.c b/drivers/mtd/nand/spi/gigadevice.c index cb1d316fc4d8..b4087767fe50 100644 --- a/drivers/mtd/nand/spi/gigadevice.c +++ b/drivers/mtd/nand/spi/gigadevice.c @@ -533,6 +533,26 @@ static const struct spinand_info gigadevice_spinand_table[] = { SPINAND_HAS_QE_BIT, SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout, gd5fxgq4uexxg_ecc_get_status)), + SPINAND_INFO("GD5F1GM9UExxG", + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x91, 0x01), + NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1), + NAND_ECCREQ(8, 512), + SPINAND_INFO_OP_VARIANTS(&read_cache_variants_1gq5, + &write_cache_variants, + &update_cache_variants), + SPINAND_HAS_QE_BIT, + SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout, + gd5fxgq4uexxg_ecc_get_status)), + SPINAND_INFO("GD5F1GM9RExxG", + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x81, 0x01), + NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1), + NAND_ECCREQ(8, 512), + SPINAND_INFO_OP_VARIANTS(&read_cache_variants_1gq5, + &write_cache_variants, + &update_cache_variants), + SPINAND_HAS_QE_BIT, + SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout, + gd5fxgq4uexxg_ecc_get_status)), }; static const struct spinand_manufacturer_ops gigadevice_spinand_manuf_ops = { |