diff options
| author | Mark Brown <broonie@kernel.org> | 2025-05-01 14:43:44 +0900 |
|---|---|---|
| committer | Mark Brown <broonie@kernel.org> | 2025-05-01 14:43:44 +0900 |
| commit | 844af9911a5d1dc41f3478dc312a404b38cbc83b (patch) | |
| tree | d6aef04723f2265235c3d7fb846e522269bacbab /arch/openrisc/mm/init.c | |
| parent | 7f91f012c1df07af6b915d1f8cece202774bb50e (diff) | |
| parent | cce34d113e2a592806abcdc02c7f8513775d8b20 (diff) | |
ASoC: stm32: sai: fix kernel rate configuration
Merge series from Olivier Moysan <olivier.moysan@foss.st.com>:
This patchset adds some checks on kernel minimum rate requirements.
This avoids potential clock rate misconfiguration, when setting the
kernel frequency on STM32MP2 SoCs.
Diffstat (limited to 'arch/openrisc/mm/init.c')
| -rw-r--r-- | arch/openrisc/mm/init.c | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/arch/openrisc/mm/init.c b/arch/openrisc/mm/init.c index be1c2eb8bb94..e4904ca6f0a0 100644 --- a/arch/openrisc/mm/init.c +++ b/arch/openrisc/mm/init.c @@ -35,6 +35,7 @@ #include <asm/fixmap.h> #include <asm/tlbflush.h> #include <asm/sections.h> +#include <asm/cacheflush.h> int mem_init_done; @@ -176,8 +177,8 @@ void __init paging_init(void) barrier(); /* Invalidate instruction caches after code modification */ - mtspr(SPR_ICBIR, 0x900); - mtspr(SPR_ICBIR, 0xa00); + local_icache_block_inv(0x900); + local_icache_block_inv(0xa00); /* New TLB miss handlers and kernel page tables are in now place. * Make sure that page flags get updated for all pages in TLB by |