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| author | Wolfram Sang <wsa+renesas@sang-engineering.com> | 2025-05-02 16:31:35 +0200 |
|---|---|---|
| committer | Wolfram Sang <wsa+renesas@sang-engineering.com> | 2025-05-02 16:31:35 +0200 |
| commit | 8e17493ea2d1c9f72e5e31160f75f8be56f79ffb (patch) | |
| tree | 0a3a6fbb8c1ec61bb08a9f612826521b5e15c1d9 /arch/openrisc/mm/init.c | |
| parent | 9c32cda43eb78f78c73aee4aa344b777714e259b (diff) | |
| parent | b1852c5de2f2a37dd4462f7837c9e3e678f9e546 (diff) | |
Merge tag 'i2c-host-fixes-6.15-rc5' of git://git.kernel.org/pub/scm/linux/kernel/git/andi.shyti/linux into i2c/for-current
i2c-host-fixes for v6.15-rc5
- imx-lpi2c: fix error handling sequence in probe
Diffstat (limited to 'arch/openrisc/mm/init.c')
| -rw-r--r-- | arch/openrisc/mm/init.c | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/arch/openrisc/mm/init.c b/arch/openrisc/mm/init.c index be1c2eb8bb94..e4904ca6f0a0 100644 --- a/arch/openrisc/mm/init.c +++ b/arch/openrisc/mm/init.c @@ -35,6 +35,7 @@ #include <asm/fixmap.h> #include <asm/tlbflush.h> #include <asm/sections.h> +#include <asm/cacheflush.h> int mem_init_done; @@ -176,8 +177,8 @@ void __init paging_init(void) barrier(); /* Invalidate instruction caches after code modification */ - mtspr(SPR_ICBIR, 0x900); - mtspr(SPR_ICBIR, 0xa00); + local_icache_block_inv(0x900); + local_icache_block_inv(0xa00); /* New TLB miss handlers and kernel page tables are in now place. * Make sure that page flags get updated for all pages in TLB by |