diff options
| author | Jason Gunthorpe <jgg@nvidia.com> | 2021-12-14 20:18:48 -0400 |
|---|---|---|
| committer | Jason Gunthorpe <jgg@nvidia.com> | 2021-12-14 20:18:48 -0400 |
| commit | 4922f0920966c28d674b03479cdcb7f3939bfbbd (patch) | |
| tree | 6a8b3972ff853fc0addcfab662d33354124f7fdb /arch/x86/include/asm/fpu/api.h | |
| parent | 20679094a0161c94faf77e373fa3f7428a8e14bd (diff) | |
| parent | 2585cf9dfaaddf00b069673f27bb3f8530e2039c (diff) | |
Merge tag 'v5.16-rc5' into rdma.git for-next
Required due to dependencies in following patches.
Signed-off-by: Jason Gunthorpe <jgg@nvidia.com>
Diffstat (limited to 'arch/x86/include/asm/fpu/api.h')
| -rw-r--r-- | arch/x86/include/asm/fpu/api.h | 6 |
1 files changed, 0 insertions, 6 deletions
diff --git a/arch/x86/include/asm/fpu/api.h b/arch/x86/include/asm/fpu/api.h index 6053674f9132..c2767a6a387e 100644 --- a/arch/x86/include/asm/fpu/api.h +++ b/arch/x86/include/asm/fpu/api.h @@ -102,12 +102,6 @@ extern void switch_fpu_return(void); */ extern int cpu_has_xfeatures(u64 xfeatures_mask, const char **feature_name); -/* - * Tasks that are not using SVA have mm->pasid set to zero to note that they - * will not have the valid bit set in MSR_IA32_PASID while they are running. - */ -#define PASID_DISABLED 0 - /* Trap handling */ extern int fpu__exception_code(struct fpu *fpu, int trap_nr); extern void fpu_sync_fpstate(struct fpu *fpu); |