diff options
| author | William Tseng <william.tseng@intel.com> | 2023-09-14 17:51:37 +0800 |
|---|---|---|
| committer | Jani Nikula <jani.nikula@intel.com> | 2023-09-20 20:16:09 +0300 |
| commit | fc3bbd576008e48d22285500c2af77c44ac31c98 (patch) | |
| tree | 9077bb54c941a6d5aa9020e2733158eaefca4561 /drivers/fpga/fpga-bridge.c | |
| parent | e356289680321c39036847b5967c26716d285c3e (diff) | |
drm/i915/dsi: let HW maintain CLK_POST
This change is to adjust TCLK-POST timing so DSI signaling can
meet CTS specification.
For clock lane, the TCLK-POST timing may be changed from
133.44 ns to 178.72 ns, which is greater than (60 ns+52*UI)
and is conformed to the CTS standard.
The computed UI is around 1.47 ns.
v2: remove the change of HS-TRAIL.
Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
Cc: Jani Nikula <jani.nikula@linux.intel.com>
Cc: Vandita Kulkarni <vandita.kulkarni@intel.com>
Cc: Suraj Kandpal <suraj.kandpal@intel.com>
Cc: Lee Shawn C <shawn.c.lee@intel.com>
Signed-off-by: William Tseng <william.tseng@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230914095137.4132029-1-william.tseng@intel.com
Diffstat (limited to 'drivers/fpga/fpga-bridge.c')
0 files changed, 0 insertions, 0 deletions