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authorChao Gao <chao.gao@intel.com>2025-09-19 15:32:41 -0700
committerSean Christopherson <seanjc@google.com>2025-09-23 09:26:30 -0700
commit42ae6448531b5106e9f29794992856e94a52b5cb (patch)
treebbbb9c1fa7f396a2bbe979a09522c4ee4960d590 /drivers/infiniband/hw/ionic/ionic_datapath.c
parent62f7533a6b3aad9d39c6098dbc3d8e7daeda9399 (diff)
KVM: nVMX: Advertise new VM-Entry/Exit control bits for CET state
Advertise the LOAD_CET_STATE VM-Entry/Exit control bits in the nested VMX MSRS, as all nested support for CET virtualization, including consistency checks, is in place. Advertise support if and only if KVM supports at least one of IBT or SHSTK. While it's userspace's responsibility to provide a consistent CPU model to the guest, that doesn't mean KVM should set userspace up to fail. Note, the existing {CLEAR,LOAD}_BNDCFGS behavior predates KVM_X86_QUIRK_STUFF_FEATURE_MSRS, i.e. KVM "solved" the inconsistent CPU model problem by overwriting the VMX MSRs provided by userspace. Signed-off-by: Chao Gao <chao.gao@intel.com> Link: https://lore.kernel.org/r/20250919223258.1604852-35-seanjc@google.com Co-developed-by: Sean Christopherson <seanjc@google.com> Signed-off-by: Sean Christopherson <seanjc@google.com>
Diffstat (limited to 'drivers/infiniband/hw/ionic/ionic_datapath.c')
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