diff options
author | Ingo Molnar <mingo@kernel.org> | 2019-12-10 10:11:00 +0100 |
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committer | Ingo Molnar <mingo@kernel.org> | 2019-12-10 10:11:00 +0100 |
commit | 2040cf9f59037aa8aec749363e69ead165b67b43 (patch) | |
tree | e9c15448e841cc493bc80b9f658d7955623e86dd /drivers/pci/controller/dwc/pcie-uniphier.c | |
parent | f66c0447cca1281116224d474cdb37d6a18e4b5b (diff) | |
parent | e42617b825f8073569da76dc4510bfa019b1c35a (diff) |
Merge tag 'v5.5-rc1' into core/kprobes, to resolve conflicts
Signed-off-by: Ingo Molnar <mingo@kernel.org>
Diffstat (limited to 'drivers/pci/controller/dwc/pcie-uniphier.c')
-rw-r--r-- | drivers/pci/controller/dwc/pcie-uniphier.c | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/drivers/pci/controller/dwc/pcie-uniphier.c b/drivers/pci/controller/dwc/pcie-uniphier.c index 3f30ee4a00b3..8fd7badd59c2 100644 --- a/drivers/pci/controller/dwc/pcie-uniphier.c +++ b/drivers/pci/controller/dwc/pcie-uniphier.c @@ -33,6 +33,10 @@ #define PCL_PIPEMON 0x0044 #define PCL_PCLK_ALIVE BIT(15) +#define PCL_MODE 0x8000 +#define PCL_MODE_REGEN BIT(8) +#define PCL_MODE_REGVAL BIT(0) + #define PCL_APP_READY_CTRL 0x8008 #define PCL_APP_LTSSM_ENABLE BIT(0) @@ -85,6 +89,12 @@ static void uniphier_pcie_init_rc(struct uniphier_pcie_priv *priv) { u32 val; + /* set RC MODE */ + val = readl(priv->base + PCL_MODE); + val |= PCL_MODE_REGEN; + val &= ~PCL_MODE_REGVAL; + writel(val, priv->base + PCL_MODE); + /* use auxiliary power detection */ val = readl(priv->base + PCL_APP_PM0); val |= PCL_SYS_AUX_PWR_DET; |