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authorMark Brown <broonie@kernel.org>2025-04-23 12:43:27 +0100
committerMark Brown <broonie@kernel.org>2025-04-23 12:43:27 +0100
commit382d4ee4455234b498f201c00bfc120dc38b78c3 (patch)
tree004c6db23c33623dd9ff5adaafe2e191748a1cbf /drivers/pwm/pwm-mediatek.c
parent7762fdab23100514e5cb612331c96bd65126ada5 (diff)
parente8ac7336dd62f0443a675ed80b17f0f0e6846e20 (diff)
regulator: max20086: Fixes chip id and enable gpio
Merge series from João Paulo Gonçalves <jpaulo.silvagoncalves@gmail.com>: I'm working on integrating a system with a MAX20086 and noticed these small issues in the driver: the chip ID for MAX20086 is 0x30 and not 0x40. Also, in my use case, the enable pin is always enabled by hardware, so the enable GPIO isn't needed. Without these changes, the driver fails to probe.
Diffstat (limited to 'drivers/pwm/pwm-mediatek.c')
-rw-r--r--drivers/pwm/pwm-mediatek.c8
1 files changed, 6 insertions, 2 deletions
diff --git a/drivers/pwm/pwm-mediatek.c b/drivers/pwm/pwm-mediatek.c
index 01dfa0fab80a..7eaab5831499 100644
--- a/drivers/pwm/pwm-mediatek.c
+++ b/drivers/pwm/pwm-mediatek.c
@@ -121,21 +121,25 @@ static int pwm_mediatek_config(struct pwm_chip *chip, struct pwm_device *pwm,
struct pwm_mediatek_chip *pc = to_pwm_mediatek_chip(chip);
u32 clkdiv = 0, cnt_period, cnt_duty, reg_width = PWMDWIDTH,
reg_thres = PWMTHRES;
+ unsigned long clk_rate;
u64 resolution;
int ret;
ret = pwm_mediatek_clk_enable(chip, pwm);
-
if (ret < 0)
return ret;
+ clk_rate = clk_get_rate(pc->clk_pwms[pwm->hwpwm]);
+ if (!clk_rate)
+ return -EINVAL;
+
/* Make sure we use the bus clock and not the 26MHz clock */
if (pc->soc->has_ck_26m_sel)
writel(0, pc->regs + PWM_CK_26M_SEL);
/* Using resolution in picosecond gets accuracy higher */
resolution = (u64)NSEC_PER_SEC * 1000;
- do_div(resolution, clk_get_rate(pc->clk_pwms[pwm->hwpwm]));
+ do_div(resolution, clk_rate);
cnt_period = DIV_ROUND_CLOSEST_ULL((u64)period_ns * 1000, resolution);
while (cnt_period > 8191) {