diff options
| author | Connor Abbott <cwabbott0@gmail.com> | 2024-04-30 11:43:16 +0100 |
|---|---|---|
| committer | Rob Clark <robdclark@chromium.org> | 2024-06-21 13:41:43 -0700 |
| commit | 90c3e2bc9ecbf3210d661fadee4c947d34a88ceb (patch) | |
| tree | 1ed3e0b28e1806daf0dcf229e4a3be19eeb85dd5 /drivers | |
| parent | d38660ebde6205ce73534a272daf2f2ef41fecef (diff) | |
firmware: qcom_scm: Add gpu_init_regs call
This will used by drm/msm to initialize GPU registers that Qualcomm's
firmware doesn't make writeable to the kernel.
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Connor Abbott <cwabbott0@gmail.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Acked-by: Bjorn Andersson <andersson@kernel.org>
Patchwork: https://patchwork.freedesktop.org/patch/592039/
Signed-off-by: Rob Clark <robdclark@chromium.org>
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/firmware/qcom/qcom_scm.c | 14 | ||||
| -rw-r--r-- | drivers/firmware/qcom/qcom_scm.h | 3 |
2 files changed, 17 insertions, 0 deletions
diff --git a/drivers/firmware/qcom/qcom_scm.c b/drivers/firmware/qcom/qcom_scm.c index 68f4df7e6c3c..0f2e628f5cac 100644 --- a/drivers/firmware/qcom/qcom_scm.c +++ b/drivers/firmware/qcom/qcom_scm.c @@ -1394,6 +1394,20 @@ int qcom_scm_lmh_dcvsh(u32 payload_fn, u32 payload_reg, u32 payload_val, } EXPORT_SYMBOL_GPL(qcom_scm_lmh_dcvsh); +int qcom_scm_gpu_init_regs(u32 gpu_req) +{ + struct qcom_scm_desc desc = { + .svc = QCOM_SCM_SVC_GPU, + .cmd = QCOM_SCM_SVC_GPU_INIT_REGS, + .arginfo = QCOM_SCM_ARGS(1), + .args[0] = gpu_req, + .owner = ARM_SMCCC_OWNER_SIP, + }; + + return qcom_scm_call(__scm->dev, &desc, NULL); +} +EXPORT_SYMBOL_GPL(qcom_scm_gpu_init_regs); + static int qcom_scm_find_dload_address(struct device *dev, u64 *addr) { struct device_node *tcsr; diff --git a/drivers/firmware/qcom/qcom_scm.h b/drivers/firmware/qcom/qcom_scm.h index 4532907e8489..484e030bcac9 100644 --- a/drivers/firmware/qcom/qcom_scm.h +++ b/drivers/firmware/qcom/qcom_scm.h @@ -138,6 +138,9 @@ int scm_legacy_call(struct device *dev, const struct qcom_scm_desc *desc, #define QCOM_SCM_WAITQ_RESUME 0x02 #define QCOM_SCM_WAITQ_GET_WQ_CTX 0x03 +#define QCOM_SCM_SVC_GPU 0x28 +#define QCOM_SCM_SVC_GPU_INIT_REGS 0x01 + /* common error codes */ #define QCOM_SCM_V2_EBUSY -12 #define QCOM_SCM_ENOMEM -5 |