clk: sunxi-ng: v3s: Assign the de and tcon clocks to the video pll

It appears (based on experimentation) that both the de and tcon clocks
need to have the same parent for the two units to work together.

Assign them both to the video pll by manually clearing the parent
selection bits (effectively setting index 0) and marking the clocks
with the CLK_SET_RATE_NO_REPARENT flag, which ensures that they will
never use a different parent.

The video pll is also a possible parent for the camera subsystem,
but it can use the dedicated isp pll if needed so there should be
no negative side-effect due to this change.

Note that ccu_mux_helper_set_parent cannot be used at this stage as
it requires the clock driver to be initialized and this configuration
is best done before the clock driver is available to consumers.

Signed-off-by: Paul Kocialkowski <paulk@sys-base.io>
Link: https://patch.msgid.link/20250704154008.3463257-2-paulk@sys-base.io
Signed-off-by: Chen-Yu Tsai <wens@csie.org>

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