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authorLucas Tanure <tanureal@opensource.cirrus.com>2021-05-25 10:08:19 +0100
committerMark Brown <broonie@sirena.org.uk>2021-05-25 16:45:03 +0100
commit1c52825c38fc4e44c61ed75a8ae32f5fa580383b (patch)
treeafa3df527c85efca7aac5e4f53105ba59d48baf1 /lib/mpi/mpiutil.c
parentd4e9889b02014a07c8dba3fbbae7205ea4084350 (diff)
ASoC: cs42l42: Fix 1536000 Bit Clock instability
The 16 Bits, 2 channels, 48K sample rate use case needs to configure a safer pll_divout during the start of PLL After 800us from the start of PLL the correct pll_divout can be set Signed-off-by: Lucas Tanure <tanureal@opensource.cirrus.com> Reviewed-by: Richard Fitzgerald <rf@opensource.cirrus.com> Message-Id: <20210525090822.64577-1-tanureal@opensource.cirrus.com> Signed-off-by: Mark Brown <broonie@sirena.org.uk>
Diffstat (limited to 'lib/mpi/mpiutil.c')
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