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| author | Bjorn Helgaas <bhelgaas@google.com> | 2019-10-09 16:07:51 -0500 |
|---|---|---|
| committer | Bjorn Helgaas <bhelgaas@google.com> | 2019-10-15 16:39:10 -0500 |
| commit | e5adf79a1d8086aefa56f48eeb08f8fe4e054a3d (patch) | |
| tree | f053b77ce7824bd10bd5f99127159eb81663b5b8 /net/lapb/lapb_timer.c | |
| parent | 751035b8dc061ae434c3311bac9cd6d0e5e00f94 (diff) | |
PCI/ATS: Cache PRI PRG Response PASID Required bit
The PRG Response PASID Required bit in the PRI Capability is read-only.
Read it once when we enumerate the device and cache the value so we don't
need to read it again.
Based-on-patch-by: Kuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@linux.intel.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Diffstat (limited to 'net/lapb/lapb_timer.c')
0 files changed, 0 insertions, 0 deletions