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| author | Sebastian Brzezinka <sebastian.brzezinka@intel.com> | 2025-08-11 09:12:39 +0000 |
|---|---|---|
| committer | Andi Shyti <andi.shyti@kernel.org> | 2025-08-18 20:32:11 -0100 |
| commit | 77a16455fae43e304e6adaf83da5b2ba6f3ad1ad (patch) | |
| tree | 0c4c4a3ddcec42b126bd3b5e4934e924e23f66ab /rust/helpers/bitops.c | |
| parent | c9932f0d604e4c8f2c6018e598a322acb43c68a2 (diff) | |
drm/i915/gt: Relocate Gen7 context-specific workarounds
CACHE_MODE_1 and CACHE_MODE_0 register should be saved and restored
as part of the context, not during engine reset. Move the related
workarounds (RC_OP_FLUSH_ENABLE, PIXEL_SUBSPAN_COLLECT_OPT_DISABLE)
from rcs_engine_wa_init() to gen7_ctx_workarounds_init() for
Gen7 platforms. This ensures the WA is applied during context
initialisation.
BSPEC: 11322, 11323
Signed-off-by: Sebastian Brzezinka <sebastian.brzezinka@intel.com>
Reviewed-by: Andi Shyti <andi.shyti@linux.intel.com>
Reviewed-by: Krzysztof Karas <krzysztof.karas@intel.com>
Signed-off-by: Andi Shyti <andi.shyti@linux.intel.com>
Link: https://lore.kernel.org/r/06cf152803ab0050e09c521ac2fc3637549860b3.1754902406.git.sebastian.brzezinka@intel.com
Diffstat (limited to 'rust/helpers/bitops.c')
0 files changed, 0 insertions, 0 deletions