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authorChen-Yu Tsai <wens@csie.org>2025-09-26 03:15:58 +0800
committerPaolo Abeni <pabeni@redhat.com>2025-10-01 10:01:34 +0200
commitd9fcb34f8b3bf793fadb591aafc76f27ecb48ff0 (patch)
tree2e80713face81cc40c39d4664fb9ddbcc980f5b3 /rust/helpers/bug.c
parent1a98f5699bd57c9b3f66ec54cc38571d5e42ffb1 (diff)
dt-bindings: net: sun8i-emac: Add A523 GMAC200 compatible
The Allwinner A523 SoC family has a second Ethernet controller, called the GMAC200 in the BSP and T527 datasheet, and referred to as GMAC1 for numbering. This controller, according to BSP sources, is fully compatible with a slightly newer version of the Synopsys DWMAC core. The glue layer around the controller is the same as found around older DWMAC cores on Allwinner SoCs. The only slight difference is that since this is the second controller on the SoC, the register for the clock delay controls is at a different offset. Last, the integration includes a dedicated clock gate for the memory bus and the whole thing is put in a separately controllable power domain. Add a compatible string entry for it, and work in the requirements for a second clock and a power domain. Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Acked-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Chen-Yu Tsai <wens@csie.org> Link: https://patch.msgid.link/20250925191600.3306595-2-wens@kernel.org Signed-off-by: Paolo Abeni <pabeni@redhat.com>
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