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| author | Dave Jiang <dave.jiang@intel.com> | 2025-08-29 11:09:19 -0700 |
|---|---|---|
| committer | Dave Jiang <dave.jiang@intel.com> | 2025-09-17 08:49:50 -0700 |
| commit | 4fde89539a18d39169a511fda00db65eeba1a8e0 (patch) | |
| tree | a4bd192256a0a83decfafc62b218e659fb441c17 /rust/helpers/build_bug.c | |
| parent | 8f5ae30d69d7543eee0d70083daf4de8fe15d585 (diff) | |
cxl: Add helper to detect top of CXL device topology
Add a helper to replace the open code detection of CXL device hierarchy
root, or the host bridge. The helper will be used for delayed downstream
port (dport) creation.
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Reviewed-by: Li Ming <ming.li@zohomail.com>
Reviewed-by: Dan Williams <dan.j.williams@intel.com>
Reviewed-by: Alison Schofield <alison.schofield@intel.com>
Reviewed-by: Robert Richter <rrichter@amd.com>
Tested-by: Robert Richter <rrichter@amd.com>
Signed-off-by: Dave Jiang <dave.jiang@intel.com>
Diffstat (limited to 'rust/helpers/build_bug.c')
0 files changed, 0 insertions, 0 deletions