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| author | Yuanfang Zhang <yuanfang.zhang@oss.qualcomm.com> | 2025-08-12 01:24:45 -0700 |
|---|---|---|
| committer | Suzuki K Poulose <suzuki.poulose@arm.com> | 2025-09-23 14:14:12 +0100 |
| commit | dcdc42f5dcf9b9197c51246c62966e2d54a033d8 (patch) | |
| tree | 8053a4c1bca7a745aa26df67a8896d8af8dd7c14 /rust/helpers/processor.c | |
| parent | 21dd3f8bc24b6adc57f09fff5430b0039dd00492 (diff) | |
coresight-etm4x: Conditionally access register TRCEXTINSELR
The TRCEXTINSELR is only implemented if TRCIDR5.NUMEXTINSEL > 0.
To avoid invalid accesses, introduce a check on numextinsel
(derived from TRCIDR5[11:9]) before reading or writing to this register.
Fixes: f5bd523690d2 ("coresight: etm4x: Convert all register accesses")
Signed-off-by: Yuanfang Zhang <yuanfang.zhang@oss.qualcomm.com>
Reviewed-by: James Clark <james.clark@linaro.org>
Reviewed-by: Mike Leach <mike.leach@linaro.org>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Link: https://lore.kernel.org/r/20250812-trcextinselr_issue-v2-1-e6eb121dfcf4@oss.qualcomm.com
Diffstat (limited to 'rust/helpers/processor.c')
0 files changed, 0 insertions, 0 deletions