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author | Nicolas Frattaroli <nicolas.frattaroli@collabora.com> | 2025-08-25 10:28:21 +0200 |
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committer | Yury Norov <yury.norov@gmail.com> | 2025-09-02 19:59:16 -0400 |
commit | 21368fcbb124d51b5d8bd8fa0a286a23c34a0888 (patch) | |
tree | c3169474ac77876583ff585b599b3bc8d20b1fa3 /rust/helpers/task.c | |
parent | a3fecb9160482367365cc384c59dd220b162b066 (diff) |
bitmap: introduce hardware-specific bitfield operations
Hardware of various vendors, but very notably Rockchip, often uses
32-bit registers where the upper 16-bit half of the register is a
write-enable mask for the lower half.
This type of hardware setup allows for more granular concurrent register
write access.
Over the years, many drivers have hand-rolled their own version of this
macro, usually without any checks, often called something like
HIWORD_UPDATE or FIELD_PREP_HIWORD, commonly with slightly different
semantics between them.
Clearly there is a demand for such a macro, and thus the demand should
be satisfied in a common header file. As this is a convention that spans
across multiple vendors, and similar conventions may also have
cross-vendor adoption, it's best if it lives in a vendor-agnostic header
file that can be expanded over time.
Add hw_bitfield.h with two macros: FIELD_PREP_WM16, and
FIELD_PREP_WM16_CONST. The latter is a version that can be used in
initializers, like FIELD_PREP_CONST.
Suggested-by: Yury Norov (NVIDIA) <yury.norov@gmail.com>
Signed-off-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
Acked-by: Jakub Kicinski <kuba@kernel.org>
Acked-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Yury Norov (NVIDIA) <yury.norov@gmail.com>
Diffstat (limited to 'rust/helpers/task.c')
0 files changed, 0 insertions, 0 deletions