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authorAkhil P Oommen <akhilpo@oss.qualcomm.com>2025-09-08 13:57:00 +0530
committerRob Clark <robin.clark@oss.qualcomm.com>2025-09-08 07:24:59 -0700
commita27d774045566b587bfc1ae9fb122642b06677b8 (patch)
tree62dc2ee4927d5f59ced5dbff4eb51e42dbe3f5cc /rust/helpers/vmalloc.c
parentac9098b1794bc4db463241db7ed090a11dcaa541 (diff)
drm/msm/adreno: Add fenced regwrite support
There are some special registers which are accessible even when GX power domain is collapsed during an IFPC sleep. Accessing these registers wakes up GPU from power collapse and allow programming these registers without additional handshake with GMU. This patch adds support for this special register write sequence. Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com> Patchwork: https://patchwork.freedesktop.org/patch/673368/ Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com>
Diffstat (limited to 'rust/helpers/vmalloc.c')
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