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| author | Vivek Pernamitta <quic_vpernami@quicinc.com> | 2025-09-12 18:18:10 +0530 |
|---|---|---|
| committer | Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com> | 2025-09-19 13:10:49 +0530 |
| commit | 54c67740fff7360b6607d02b8499d09b944b3fda (patch) | |
| tree | dbfc9a60fd11bc11f3db71efefaabc41aa4a9973 /rust/kernel/alloc/allocator/iter.rs | |
| parent | aa1a0e93ed21a06acb7ca9d4a4a9fce75ea53d0c (diff) | |
bus: mhi: host: pci_generic: Set DMA mask for VFs
VFs in devices like QDU100 are capable of accessing host memory up to 40
bits, compared to 32 bits used by PFs and other non-SR-IOV capable MHI
devices.
To support this, configure `dma_mask` independently for PFs and VFs, by
introducing a new 'vf_dma_data_width' member in 'mhi_pci_dev_info' struct
and set it to 40 for QDU100.
Signed-off-by: Vivek Pernamitta <quic_vpernami@quicinc.com>
[mani: reworded subject and description]
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com>
Link: https://patch.msgid.link/20250912-uevent_vdev_next-20250911-v4-6-fa2f6ccd301b@quicinc.com
Diffstat (limited to 'rust/kernel/alloc/allocator/iter.rs')
0 files changed, 0 insertions, 0 deletions